The field of the invention relates generally to hardware logic emulation systems used for verification of integrated circuit and electronic system designs and more particularly to an method of improving the timing characteristics of such a hardware logic emulation system.
Hardware logic emulation systems are known devices that implement a user""s design in a plurality of programmable integrated circuits. Such logic emulation systems are available from various vendors, including Quickturn Design Systems, Inc., San Jose, Calif., United States of America, which is the assignee of the present invention. Typical emulation system utilize either programmable logic chips or processor chips which are programmably interconnected. In either case, the user""s design must be partitioned into smaller portions. In programmable logic chip (e.g., field programmable gate array, or FPGA) based emulation systems, the logic contained in the user""s design is programmed into the logic chip. In processor-based emulation systems, the user""s design is processed so that its functionality appears to be created in the processors by calculating the outputs of the design. The logic itself is not implemented in a processor-based emulation system. Examples of hardware logic emulation systems can be seen in, e.g., U.S. Pat. Nos. 5,109,353, 5,036,473, 5,475,830 and 5,960,191. U.S. Pat. Nos. 5,109,353, 5,036,473, 5,475,830 and 5,960,191 are incorporated herein by reference.
The user""s design is usually provided in the form of a netlist description of the design. A netlist description (or xe2x80x9cnetlistxe2x80x9d, as it is referred to by those of ordinary skill in the art) is a description of the integrated circuit""s components and electrical interconnections between the components. The components include all those circuit elements necessary for implementing a logic circuit, such as combinational logic (e.g., gates) and sequential logic (e.g., flip-flops and latches). In prior art emulation systems such as those manufactured and sold by Quickturn Design Systems, Inc., San Jose, Calif., the netlist is compiled such that it is placed in a form that can be used by the emulation system. Thus, after compilation, the netlist description of the user""s design has been processed such that an xe2x80x9cemulation netlistxe2x80x9d is created. An emulation netlist is a netlist that can be programmed into the programmable resources of the emulation system.
The timing characteristics of the user""s logic design is very important to the design and is given a tremendous amount of attention during the design phase. The timing characteristics of that same design when programmed into the hardware logic emulation system, however, is often changed from the timing characteristics of the design. Many factors contribute to this phenomenon, but the largest contributor is the fact that the user""s design is partitioned and implemented in many different integrated circuits. Thus, while a user""s design may be for a single integrated circuit chip, the emulator may implement that same design on hundreds of programmable chips. Such an implementation dramatically increases the amount of wiring and overhead associated with a design. Thus, clock paths become much larger and complicated when the user""s design is implemented in a hardware logic emulation system. Moreover, a user""s design often has multiple clocks, which complicates matters even further.
The most common clock error in an emulation system is the hold time violation. A hold time violation can occur if a transmitting device removes a data signal before a receiving device had properly saved it into a flip-flop or latch. Thus, the D input of a flip-flop must be stable for a short time both before and after a gating edge transition of the flip-flop""s clock pin. The required time before clock transition is called the setup-time, and the required time after the edge transition is called the hold-time.
There are several prior art methods for attempting to eliminate, or at least, minimize hold time violations in emulation systems. In one such prior art method, an auxiliary flip-flop is placed at the data input of any storage element in the user""s design. These flip-flops were clocked with a special signal that is synchronized and phase shifted relative to the design clocks. A problem with this prior art method is that it can be difficult to derive the delayed clock signal (i.e., the special signal) in a multiple clock design. Moreover, requiring the use a auxiliary flip-flops dramatically increases the size of the design that must be implemented in the emulator, which reduces the amount of user-logic that can be emulated. In addition, the emulation speed is reduced. Finally, such a method will not work for latch-based designs. Note that this method is disclosed in U.S. Pat. No. 5,259,006.
Another prior art method of reducing or eliminating hold time violations was to compile the design, determine which clock paths were experiencing hold time violations (which could be done using timing analysis tools), inserting delay elements into that delay path and recompiling the design. This method worked, but was cumbersome and slow. Examples of this method are disclosed in U.S. Pat. No. 5,475,830.
Yet another prior art method was an attempt to place the entire clock cone into a single chip. Every flip-flop input, as well as every design output, defines a cone. When the entire clock cone is placed in a single chip, the clock path delays t(C- greater than C1), t(C- greater than C2) consists entirely of the intra-chip delay with a low upper boundary approximation, which allows adding a relatively small additional data path delay without recompilation. Examples of this method are disclosed in U.S. Pat. Nos. 5,475,830 and 5,452,239.
Thus, while this prior art method improved on delay insertion, it is not without problems. One such problem with this method is that if the clock cone is too big, which is a common occurrence, the user is asked to prune the clock cone manually by marking the nets that are not really part of the clock path (i.e., clock qualifiers). Many user designs require substantial amounts of manual clock path pruning, which is undesirable. Additionally, there is no guarantee that this method will eliminate hold time violations.
As seen from the above, prior art methods of eliminating hold time violations were usually effective, but came at high cost. Thus, prior art methods developed to resynthesize the clock paths of the user""s design. One such method was to switch from gated clock logic to clock-enable logic that is controlled by the input clock C directly. Like the other prior art methods, this method was very time and memory consuming. Another problem with this method was that it does not work with multiple input clocks that control the same gated clock.
There has been a long felt need for a method that automatically eliminates hold time violations that has guaranteed success. In addition, there has been a long felt need for a method that eliminates hold time violations without requiring the user to provide data that would characterize internal design nets, does not slow emulation speed, does not use too many resources (i.e., does not substantially reduce emulator capacity), and allows emulation of designs having multiple asynchronous clocks.
The present invention provides a novel method for resynthesizing gated clocks present in a logic design that will be programmed into a hardware logic emulation system to avoid hold time violations. A clock cone comprises a plurality of clock cone nets and at least one input clock. The logic design comprises a plurality data path nets. In one embodiment of the present invention, the method comprises generating predicting logic that predicts which edges of the at least one input clock may cause a hold time violation on a gated clock. Then, outputs from the predicting logic are connected to a gated clock resolution circuit. The gated clock resolution circuit outputs a resynthesized gated clock free of hold time violations.
In another embodiment of the present invention, the step of generating predicting logic comprises creating a bit field corresponding to each of the plurality of clock cone nets. The bit field comprises data fields indicating potential behavior of the corresponding net in response to a rising edge of the at least one input clock and a falling edge of said at least one input clock. A data path bit field is created that corresponds to each of the data path nets. The data path bit field comprises data fields indicating whether a positive edge of one of the at least one input clock may cause a change on the data path nets or whether a negative edge of one of the at least one input clock may cause a change on the data path nets. The bit field corresponding to each of the plurality of clock cone nets is compared with the data path bit field for each storage element in the logic design, thereby creating a future bit field. The future bit field contains data indicating whether a net is susceptible to a hold time violation for the particular edge of one of the at least one input clock or is not susceptible to a hold time violation for the particular edge of one of the at least one input clock. Predicting logic is then built for each net that is susceptible to a hold time violation.
The above and other preferred features of the invention, including various novel details of implementation and combination of elements will now be more particularly described with reference to the accompanying drawings and pointed out in the claims. It will be understood that the particular methods and circuits embodying the invention are shown by way of illustration only and not as limitations of the invention. As will be understood by those skilled in the art, the principles and features of this invention may be employed in various and numerous embodiments without departing from the scope of the invention.